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24LCS21A
3.1
Bidirectional Mode Bus
Characteristics
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
The following bus protocol has been defined:
? Data transfer may be initiated only when the bus
is not busy.
? During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
conditions is determined by the master device and is
theoretically unlimited, although only the last eight will
be stored when doing a write operation. When an
overwrite does occur it will replace data in a first-in first-
out (FIFO) fashion.
the data line while the clock line is high will be
Note:
Once switched into Bidirectional mode, the
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-4).
3.1.1 BUS NOT BUSY (A)
Both data and clock lines remain high.
3.1.2 START DATA TRANSFER (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
24LCS21A will remain in that mode until
power is removed. Removing power is the
only way to reset the 24LCS21A into the
Transmit-Only mode.
3.1.5 ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
commands must be preceded by a Start condition.
Note:
The 24LCS21A does not generate any
3.1.3
STOP DATA TRANSFER (C)
Acknowledge bits if an internal
programming cycle is in progress.
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
3.1.4
DATA VALID (D)
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition.
FIGURE 3-4:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
(A)
(B)
(D)
(D)
(C)
(A)
SDA
Start
Condition
? 2007 Microchip Technology Inc.
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
DS21161H-page 7
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